(A) Field of the Invention
The present invention relates to a trench capacitor and a method for preparing the same, and more particularly, to a trench capacitor for a dynamic random access memory and a method for preparing the same.
(B) Description of the Related Art
A memory cell of the dynamic random access memory (DRAM) includes an access transistor and a storage capacitor, wherein the source of the access transistor is electrically connected to a top electrode of the storage capacitor, and a bottom electrode of the storage capacitor is biased to a positive voltage. Particularly, the more the electric charges being stored in the storage capacitor, the less the occurrence of the error generated from the interpretation of data by a sensing amplifier due to the influence of noise. Therefore, current memory cells of the DRAM use 3-D capacitors, such as stacked capacitors or trench capacitors, to increase electric charges of the storage capacitor.
FIG. 1 is a cross-sectional view of a semiconductor wafer 10 for DRAM. The semiconductor wafer 10 comprises a substrate 12, two trenches 14 positioned in the substrate 12, a bottom electrode 16 positioned on the outer surface of the trench 14, a dielectric layer 18 positioned on the inner surface of the trench 14, an top electrode 20 positioned on the surface of the dielectric layer 18, a collar oxide layer 22 positioned on the inner surface of the trench 14, a buried conductive strap 24 positioned on the top electrode 20 and a shallow trench isolation (STI) 26 filled with dielectric material. A conductive diffusion region 28 is formed at the side of the buried conductive strap 24 to electrically connect the buried conductive strap 24 to a drain electrode/source electrode 32 of the access transistor. The bottom electrode 16, the dielectric layer 18 and the top electrode 20 in each trench 14 form a capacitive structure 30. The shallow trench isolation 26 is used to prevent two neighboring capacitive structures 30 from being a short circuit.
To avoid the two capacitive structures 30 being a short circuit and to ensure that an identical contact area between the buried conductive strap 24 and the corresponding top electrode 20 is achieved so as to obtain identical contact resistance, the position of the shallow trench isolation 26 must be precisely controlled. In addition, as the integration density of integrated circuit increases rapidly, the interval between the two capacitive structures 30 reduces correspondingly, i.e., the lateral width of the shallow trench isolation 26 must be reduced. However, the lithographic process, which is used to define the position and the size of the shallow trench isolation 26, tends to generate misalignment as the size shrinks. Consequently, the position of the shallow trench isolation 26 deviates from the predetermined position due to the misalignment of the lithographic process, which results in the occurrence of short circuit between the two capacitive structures 30. That also leads to different contact area (contact resistance) between the buried conductive strap 24 and the corresponding top electrode 20 for the two capacitive structures 30.